The present invention relates to a semiconductor device, such as a positive channel metal-oxide-semiconductor (PMOS) transistor, and a fabricating method thereof.
FIG. 1A is a cross-sectional view of a positive channel metal-oxide-semiconductor (PMOS) transistor illustrating a source/drain impurity ion implantation process according to the related art. FIG. 1B is a cross-sectional view of a PMOS transistor illustrating an annealing process after the source/drain impurity ion implantation process according to the related art.
The PMOS transistor according to the related art is formed as follows. At first, a shallow trench isolation (STI) layer 101 is formed on a semiconductor substrate 100, such as a silicon substrate, in order to isolate semiconductor devices from one another, as shown in FIG. 1A. Then, an implantation process is performed to form an N-well 121 on semiconductor substrate 100.
After a gate insulation layer 123, made of a silicon oxide layer, is formed on semiconductor substrate 100, a poly silicon layer is deposited on gate insulation layer 123 to form a gate electrode 125. The poly silicon layer and the silicon oxide layer formed on a gate area of semiconductor substrate 100 are patterned through a photolithography process and an etching process by forming a patterned photoresist layer (not shown) on the poly silicon layer. That is, gate electrode 125 and gate insulation layer 123 are formed by etching, except the gate area, the poly silicon layer and the silicon oxide layer formed on semiconductor substrate 100 using the patterned photoresist layer as an etching mask.
A lightly doped drain (LDD) area 127 is formed in active areas at both sides of gate electrode 125 on semiconductor substrate 100 by implanting low-density impurities.
An insulation layer is formed on the entire surface of semiconductor substrate 100 to cover gate electrode 125. A spacer 131 is formed on side walls of gate electrode 125 and gate insulation layer 123 by etching the insulation layer. A source/drain area 133 is formed at both sides of spacer 131 on semiconductor substrate 100 by ion-implanting high density impurities.
Spacer 131 may be made of a nitride layer. In addition, a tetra ethyl ortho silicate (TEOS) 129 may be formed at the bottom of the nitride layer.
In order to form source/drain area 133 in the PMOS transistor, high density impurities, such as Boron ions, may be used.
Recently, the junction depth of source/drain area 133 has been reduced from about 90 nm to about 20 nm in the impurity ion implantation process for forming source/drain area 133 of the PMOS transistor. In order to satisfy such a reduced junction depth, the implantation process needs to be performed at a low energy of about 1 KeV to 5 KeV.
Since Boron (B) ions have a high diffusivity, in an annealing process for activating the high density Boron ions in source/drain area 133, Boron ions may be out-diffused even if the ion implantation process is performed with a low ion implantation energy. The speed of the PMOS transistor thus becomes slower, because the out-diffused Boron ions prevent the impurities to be ion-implanted in source/drain area 133 from reaching a desired implantation level.